Location and Hours:
CADathlon Brasil 2023 will take place at the Computer Laboratory (LAB-2), Computer Block, first floor,
Campus João Pessoa, at Avenida Primeiro de Maio, 720, of the Federal Institute of Paraíba
(https://goo.gl/maps/ ozREAMgSSwhNGgwTA), Bairro Jaguaribe in João Pessoa/PB, in a single and
continuous session, on August 8, 2023.
Start time: 9:00 am
End time: 18:00

Participants may only leave the room to go to the restroom, subject to the authorization of the members of the
CADathlon organization.
The CADathlon organization will offer free meals to participants:

• From 9 am to 11 am: coffee-break: seasonal fruits (banana and apple); dreaded breads (chicken with
  cream cheese, catupiry and turkey breast with ricotta); croquettes (chicken drumstick and white cheese
  puffs) and cakes (chocolate and roll);
• At 1pm, a lunch box will be served: beef stroganoff with rice and straw potatoes, soda, mini salad
  (sauce), fruit, a bonbon;
• At 3:30 pm 5:00 pm: coffee-break: coffee-break: seasonal fruits (banana and apple); dreaded breads
  (chicken with cream cheese, catupiry and turkey breast with ricotta); croquettes (chicken drumstick and
  kingdom cheese puffs) and cakes (chocolate and roll)

Note: If you are a vegetarian or have a specific diet (lactose intolerance, wheat flour intolerance, etc.),
please let us know as soon as possible by email.

Result Disclosure
The result will be announced directly to all teams by email, between the end of the CADathlon session and the
morning of August 9, 2023.

Award
The awarding of the teams that win first and second place will take place at the official dinner of the SBC
Congress, on the evening of August 9, 2023 (details will be sent soon).
The two winning teams will receive tickets to attend the dinner, as part of the award.

Rules and General Observations About the Competition Session:
1 – There will be ONE computer per team, which will be offline (without internet) during the race;
2 – The use of electronic devices will NOT be allowed during the competition, except the computer
provided by the organization;
3 – The problem statements will be in a specific folder on the supplied computer;4 – It is allowed to consult any physical material (books, articles, notebooks, documentation, etc.)
taken by the duo. Articles cited in the basic literature will be available on the computer provided by the
organization, in a specific folder;
5 – The problems must be solved using the C++ and Python programming languages, as specified in the
respective statements;
6 – Arrive at the location where the CADathlon will be held no less than 15 minutes in advance. Carefully
plan your travel time;
7 – The session will start promptly at 9:00 am, and general instructions will be given in the first few
minutes.

IMPORTANT: Considering rules 2 and 4, you must bring all material you deem necessary for solving the problems
(basic literature articles will be available offline along with the problem code). The problems will be in C++ and
Python languages. To make it easier, we have prepared a list of some libraries that can be used by problems:

C++: algorithm, array, assert.h, bitset, boost/filesystem.hpp, boost/program_options.hpp, cassert, cctype,
climits, cmath, cstdlib, cstring, exception, fstream, functional, iostream, limits, map, math. h, numeric, ostream,
queue, stack, stdexcept, stdio.h, stdlib.h, string, unordered_map, unordered_set, utility, vector

Python: sys

Themes of Problems and Basic Literature:

Problem #1: Circuit Design & Analysis.
Subject: Static Timing Analsys
Bibliography:
[1] Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu, “VLSI Physical Design: From Graph
Partitioning to Timing Closure”. Editora Springer Dordrecht, 1a. Edição – Chapter 8: Timing Closure,
2011. (https://doi.org/10.1007/978-90-481-9591-6)

Problem #2: Physical Design (& Design for Manufacturability)
Subject: Tap assignment for gated clock network
Bibliography:
[1] W.-H. Chen, C.-K. Wang, H.-M. Chen, Y.-C. Chou, C.-H. Tsai, “A Comparative Study on
Multisource Clock Network Synthesis”, Proc. SASIMI, pp. 141-145, 2016.

Problem #3: Logic & High-Level Synthesis
Subject: Boolean Function Manipulation by Quantification
Bibliography: No specific reference is provided

Problem #4: System Design & Analysis
Subject: Regression Set Construction
Bibliography:
[1] Shady Copty, Shai Fine, Shmuel Ur, Elad Yom-Tov, Avi Ziv, “A probabilistic alternative to
regression suites”, Theoretical Computer Science, Volume 404, Issue 3, 2008, Pages 219-234, ISSN
0304-3975. (https://doi.org/10.1016/j.tcs.2008.03.020)

Problem #5: Functional Verification & Testing
Subject: Circuit Rank-Ordering for Logic Simulation
Bibliography:
[1] Digital Logic Testing and Simulation, Miczo A. (2nd edition) – Chapter 2: Simulation

Problem #6: Future technologies (Bio-EDA, Security, AI, etc.)
Subject: NPN boolean function identification
Bibliography:
[1] M. D. Vieira et al., “Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots”, in
IEEE Design & Test, vol. 39, no. 6, pp. 147-155, Dec. 2022, doi: 10.1109/MDAT.2022.3189814.